View TJA1082_132993.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www..com
TJA1082
FlexRay node transceiver
Rev. 01 -- 1 July 2009 Preliminary data sheet
1. General description
The TJA1082 FlexRay node transceiver is compatible with the FlexRay electrical physical layer specification V2.1 Rev. B (see Ref. 1). It also incorporates features and parameters anticipated to be included in V3.0, currently being finalized. It is primarily intended for communication systems operating at between 2.5 Mbit/s and 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1082 offers an optimized solution for Electronic Control Unit (ECU) applications that do not need enhanced power management and are typically switched by ignition or activated by a dedicated wake-up line. The TJA1082 provides differential transmit capability to the network and differential receive capability to the FlexRay controller. It offers excellent EMC performance as well as high ESD protection. The TJA1082 actively monitors system performance using dedicated error and status information (readable by any microcontroller), as well as internal voltage and temperature monitoring.
2. Features
2.1 Optimized for time triggered communication systems
I I I I I I Compliant with Electrical Physical Layer specification 2.1 Rev. B Automotive product qualification in accordance with AEC-Q100 (Grade 1) Data transfer at 2.5 Mbit/s, 5 Mbit/s and 10 Mbit/s Supports 60 ns minimum bit time at 400 mV differential voltage Very low ElectroMagnetic Emission (EME) to support unshielded cable Differential receiver with high common-mode range for excellent ElectroMagnetic Immunity (EMI) I Auto I/O level adaptation to host controller supply voltage VIO I Can be used in 14 V and 42 V powered systems I Instant shut down interface (BGE pin)
2.2 Low power management
I Very low current consumption in Standby mode I Remote wake-up via wake-up symbol or dedicated FlexRay data frames on the bus lines
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
2.3 Diagnosis and robustness
I Enhanced supply voltage monitoring on VCC and VIO I Two error diagnosis modes: status register readout via Serial Peripheral Interface (SPI) or simple error indication via ERRN pin I Overtemperature detection I Short-circuit detection on bus lines I Power-on flag I Clamping diagnosis for pins TXEN and BGE I Bus pins protected against 8 kV ESD pulses according to IEC61000-4 and HBM I Bus pins protected against transients in automotive environment (ISO 7637 class C compliant) I Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground I Maximum differential voltage between pins BP or BM and any other pin of 60 V I Bus lines remain passive when the transceiver is not powered I No reverse currents from the digital input pins to VIO or VCC when the transceiver is not powered I Two error diagnosis modes: N Status register readout via SPI N Simple error indication via ERRN pin
2.4 FlexRay conformance classes
I Bus driver - bus guardian interface I Bus driver logic level adaptation
3. Ordering information
Table 1. Ordering information Package Name TJA1082TT TSSOP14 Description plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT402-1 Type number
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
2 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
4. Block diagram
VCC
14
VCC UNDERVOLTAGE DETECTION
VIO
1
VIO UNDERVOLTAGE DETECTION OVERTEMPERATURE DETECTION
TXEN TIMEOUT TXEN 3 I/O
13 TXD 2 TRANSMITTER I/O 12
BP BM
I/O 6
STBN
I/O
STATE MACHINE
ERRN
10
I/O
BGE
5
I/O
SDO
8
I/O LOW-POWER RECEIVER I/O SPI BUS ERROR
SCSN
9
SCLK
7
I/O
ACTIVITY DETECTION
NORMAL RECEIVER
RXD
4
I/O
MUX
11 GND
015aaa000
Fig 1. Block diagram
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
3 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
5. Pinning information
5.1 Pinning
VIO TXD TXEN RXD BGE STBN SCLK
1 2 3 4 5 6 7
015aaa001
14 VCC 13 BP 12 BM
TJA1082TT
11 GND 10 ERRN 9 8 SCSN SDO
Fig 2. Pin configuration
5.2 Pin description
Table 2. VIO TXD TXEN RXD BGE STBN SCLK SDO SCSN ERRN GND BM BP VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin description Type P I I O I I I O I O P I/O I/O P Description supply voltage for VIO voltage level adaptation transmit data input; internal pull-down transmitter enable input; when HIGH transmitter disabled; internal pull-up receive data output bus guardian enable input; when LOW transmitter disabled; internal pull-down mode control input; transceiver in Normal mode when HIGH; internal pull-down SPI clock signal; internal pull-up SPI data output SPI chip select input; internal pull-up/pull-down error diagnosis output and wake-up indication ground bus line minus bus line plus supply voltage (+5 V) Symbol Pin
6. Functional description
6.1 Power modes
The TJA1082 features three power modes: Normal, Standby and Power-off. Normal and Standby modes can be selected via the STBN input (HIGH for Normal mode) once the transceiver has been powered up. See Table 3 for a detailed description of pin signaling in the three power modes.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
4 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 3. Mode
Pin signalling in the different power modes STBN UV at UV VIO at VCC HIGH no no ERRN LOW HIGH error error flag flag reset set wake wake flag flag set reset RXD LOW HIGH SDO Biasing BP, BM UV-det Transmitter Lowpower receiver enabled[1]
Normal
Standby
LOW
no
no
LOW
no
yes[3] wake wake flag flag set[4] reset[4] yes[3] error error flag flag set reset LOW LOW highimpedance yes[3] yes
VCC / 2 highbus bus DATA_ DATA_1 impedance (in simple or idle 0 error wake wake GND indication flag flag mode) or set reset enabled (in wake wake SPI mode) flag flag set[4] reset[4] wake flag set[4] LOW LOW HIGH wake flag reset[4] highimpedance GND[7]
enabled enabled
disabled enabled[2]
disabled
HIGH no
X X Power-off[6] X
yes[5] no yes[5] X[5]
enabled[2] disabled disabled disabled
[1] [2] [3] [4] [5] [6] [7]
The wake flag is set if a valid wake-up event is detected while switching to Standby mode. The wake flag is set if a valid wake-up event is detected. Vuvd(VCC) > VCC > Vth(det)POR. Pins ERRN and RXD will reflect the state of the wake flag prior to the undervoltage event. The internal signals at pins STBN, BGE and TXD are set LOW; the internal signals at pins TXEN, SCLK and SCSN are set HIGH. VCC < Vth(rec)POR at power-up and VCC < Vth(det)POR at power-down (see Figure 6 and Figure 7). Except when VCC = 0; in this case the biasing of BP and BM is floating.
6.1.1 Normal mode
In Normal mode, the transceiver transmits and receives data via the bus lines BP and BM. The transmitter and the normal receiver are enabled, along with the undervoltage detection function. The timing diagram for Normal mode is illustrated in Figure 3.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
5 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
TXD
BGE
TXEN
BP BM
RXD
015aaa002
Fig 3. Timing diagram in Normal mode
Table 4 describes the behavior of the transmitter in Normal mode, when the temperature flag (TEMP HIGH) is not set and with no time-out on pin TXEN. Transmitter behavior is illustrated in Figure 14.
Table 4. BGE L X H H X H L L Transmitter operation in Normal mode TXEN TXD X X H L Bus state idle idle DATA_1 DATA_0 Transmitter transmitter is disabled transmitter is disabled transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH
The transmitter is activated during the first LOW level on pin TXD while pin BGE is HIGH and pin TXEN is LOW. In Normal mode, the normal receiver output is connected directly to pin RXD (see Table 5). Receiver behavior is illustrated in Figure 15.
Table 5. Bus state DATA_0 DATA_1 idle Behavior of normal receiver in Normal mode RXD L H H
When VIO and VCC are within their operating ranges, pin ERRN indicates the status of the error flag. See Section 6.7 for a detailed description of error signalling in Normal mode. 6.1.1.1 Bus activity and idle detection In Normal mode, bus activity and bus idle are detected as follows:
TJA1082_1 (c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
6 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
* Bus activity is detected when the absolute differential voltage on the bus lines is
higher than Vi(dif)det(act) for tdet(act)(bus): - If the differential voltage on the bus lines is higher than VIH(dif) after bus activity has been detected, pin RXD goes HIGH. - If the differential voltage on the bus lines is lower than VIL(dif) after bus activity has been detected, pin RXD goes LOW.
* Bus idle is detected when the absolute differential voltage on the bus lines is lower
than Vi(dif)det(act) for tdet(idle)(bus). This results in pin RXD being switched HIGH or staying HIGH.
6.1.2 Standby mode
Standby mode is a low-power mode featuring very low current consumption. In Standby mode, the transceiver is unable to transmit or receive data since both the transmitter and the normal receiver are switched off. The low-power receiver is activated to monitor the bus for wake-up activity, provided an undervoltage has not been detected on pin VCC. The low power receiver is deactivated if an undervoltage is detected on pin VCC - with the result that the wake flag will not be set if a wake-up pattern or dedicated data frame is received. Pins ERRN and RXD indicate the status of the wake flag when VIO and VCC are within their operating ranges. See Table 3 for a description of pins ERRN and RXD when an undervoltage is detected on pin VIO or pin VCC. The status register cannot be read via the SPI interface if an undervoltage is detected on pin VIO. The BGE input has no effect In Standby mode.
6.1.3 Power-off mode
The transmitter and the two receivers (normal and low-power) are deactivated in Power-off mode. As a result, the wake flag will not be set if a wake-up pattern or dedicated data frame is received. If the voltage at VCC rises above Vth(rec)POR, the transceiver switches to Standby mode and the digital section is reset. If VCC subsequently drops below Vth(det)POR, the transceiver reverts to Power-off mode (see Section 6.2). The status register cannot be read via the SPI interface in Power-off mode.
6.1.4 State transitions
Figure 4 shows the TJA1082 state transition diagram. The timing diagram for the ERRN indication signal during transitions between Normal and Standby modes, when the error flag is set and the wake flag is not set, is illustrated in Figure 5 and described in Table 6.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
7 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
NORMAL
(STBN -> HIGH while UV flags cleared) or (UV flags cleared while STBN = HIGH)
STBN -> LOW or UVVCC flag set or UVVIO flag set
STANDBY
VCC > Vth(rec)POR
VCC < Vth(det)POR
power-up
POWER OFF
015aaa004
Fig 4. State transitions diagram
20 s
STBN
td(norm-stb)
td(stb-norm)
ERRN
015aaa003
Fig 5. State transitions timing (bus error flag set)
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
8 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 6. State transitions indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition Normal to Standby UVVIO flag[1] cleared set cleared Standby to Normal cleared cleared cleared Standby to Power-off Power-off to Standby
[1]
UVVCC flag[1] cleared cleared set cleared cleared cleared set set
wake flag[1] cleared cleared cleared 1 cleared 1 cleared 1 cleared X X
PWON flag[1] STBN cleared cleared cleared 2 cleared 2 cleared 2 cleared X 1 set L H H H H H X X
VCC level VCC > Vuvd(VCC) VCC > Vuvd(VCC) Vuvd(VCC) > VCC > Vth(det)POR VCC > Vuvd(VCC) VCC > Vuvd(VCC) Vuvd(VCC) > VCC > Vth(det)POR VCC < Vth(det)POR VCC > Vth(rec)POR
X X
See Table 7 for set and reset conditions of all flags.
6.2 Power-up and power-down behavior
6.2.1 Power-up
The TJA1082 has two supply pins: VCC (+5 V) and VIO (for the voltage level adaptation). The ramp up of the different power supplies can vary, depending on the state or value of a number of signals and parameters.The power-up behavior of the TJA1082 is not affected by the sequence in which power is supplied to these pins or by the voltage ramp up. As an example, Figure 6 shows one possible power supply ramp-up scenario. The digital section of the TJA1082 is supplied by VCC. The voltage on pin VCC ramps up before the voltage on pin VIO. As long as the voltage on VCC remains below the power-on reset recovery threshold, Vth(rec)POR, the internal state machine will not be active and the transceiver will be totally passive, remaining in Power-off mode. As soon as the voltage crosses the Vth(rec)POR threshold, the internal state machine starts running, setting the PWON flag and switching the TJA1082 to Standby mode. This initializes the VCC and VIO under-voltage flags to the set state (since both VCC and VIO are actually in undervoltage state just after power-on). Once both VIO and VCC have reached their operating ranges in Standby mode (above Vuvd(VIO) and Vuvd(VCC) respectively), the under-voltage flags are reset and the transceiver enters the mode indicated by STBN (Normal or Standby).
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
9 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Power-off
Standby
Normal
Vth(det)POR VCC
Vuvd(VCC) Vth(rec)POR Vuvd(VIO)
VIO
STBN
RXD
ERRN
015aaa005
Fig 6. Power-up behavior (example)
6.2.2 Power-down
The behavior of the TJA1082 during power-down is illustrated in Figure 7.
Normal
Standby Vuvd(VCC)
Power-off
VCC
Vth(rec)POR Vuvd(VIO)
Vth(det)POR
VIO
STBN
RXD
ERRN
015aaa006
Fig 7. Power-down behavior (example)
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
10 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
6.3 Remote wake-up
6.3.1 Bus wake-up via wake-up pattern
A valid remote wake-up event occurs when a wake-up pattern is received. A wake-up pattern consists of at least two consecutive wake-up symbols. A wake-up symbol consists of a DATA_0 phase lasting longer than tdet(wake), followed by an idle phase lasting longer than tdet(wake)idle, provided both wake-up symbols occur within a time span of tdet(wake)tot (see Figure 8). The transceiver will also wake up if the idle phases are replaced by DATA_1 phases.
wake-up
Vdif (mV) +425 0 -425
< tdet(wake)tot > tdet(wake)idle > tdet(wake)idle
> tdet(wake)DATA_0
> tdet(wake)DATA_0
> tdet(wake)idle +425 0 -425 > tdet(wake)DATA_0 wake-up symbol
> tdet(wake)idle
> tdet(wake)DATA_0 wake-up symbol
wake-up pattern
015aaa007
Fig 8. Bus wake-up timing
The wake-up mechanism of the TJA1082 follows the state transition diagram shown in Figure 9. See Ref. 1 for more details of the wake-up mechanism.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
11 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
power on Wait L' Data_1 or idle on bus Data_0 for longer than tsup(int)wake tdet(wake)idle expired Wait S' Data_0 on bus Data_1 or idle for longer than tsup(int)wake tdet(wake)Data_0 expired tdet(wake)tot expired Wait A' Data_1 or idle on bus Data_0 for longer than tsup(int)wake tdet(wake)idle expired tdet(wake)tot expired Wait B' Data_0 on bus Data_1 or idle for longer than tsup(int)wake tdet(wake)tot expired Wait C' tdet(wake)Data_0 expired Data_1 or idle on bus Data_0 for longer than tsup(wake)int Wait state C tdet(wake)tot expired Wake-up! tdet(wake)idle expired
015aaa008
start tdet(wake)idle Initial state
start tdet(wake)Data_0 Start state
tdet(wake)total expired
start tdet(wake)idle tdet(wake)total expired Wait state A
start tdet(wake)Data_0 Wait state B
start tdet(wake)idle
tdet(wake)total expired
Fig 9. Wake-up state machine
6.3.2 Bus wake-up via dedicated FlexRay data frame
The TJA1082 wake flag is set when a dedicated data frame emulating a valid wake-up pattern, as shown in Figure 10, is received. The Data_0 and Data_1 phases of the emulated wake-up symbol are interrupted by the Byte Start Sequence (BSS) preceding each byte in the data frame. With a data rate of 10 Mbit/s, the interruption will have a maximum duration of 130 ns and will not prevent the transceiver from recognizing the wake-up pattern in the payload. For longer interruptions at lower data rates (5 Mbit/s and 2.5 Mbit/s), the wake-up pattern should be used (see Section 6.3.1). The wake flag will not be set if an invalid wake-up pattern is received. See Ref. 1 for more details on invalid wake-up patterns.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
12 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Vdif 130 ns +1500 0V -1500 770 870 870 ns ns ns 5 s 130 130 ns ns 5 s 5 s 5 s
015aaa097
870 ns 870 ns
wake-up
The duration of each interruption is 130 ns. The transition time from DATA_0 to DATA_1 and vice versa is about 20 ns. The TJA1082 wake-up flag is set on receipt of the following frame payload: 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
Fig 10. Minimum bus pattern for bus wake-up via dedicated FlexRay data frame
6.4 Bus error detection
The TJA1082 detects the following bus errors during transmission:
* * * * *
Short-circuit BP-BM at the ECU connector or on the bus Short-circuit BP-GND at the ECU connector or on the bus Short-circuit BM-GND at the ECU connector or on the bus Short-circuit BP-VCC at the ECU connector or on the bus Short-circuit BM-VCC at the ECU connector or on the bus
The bus error flag is not set when a wake-up pattern or a FlexRay Collision Avoidance Symbol (CAS) is being transmitted or received.
6.5 Fail silent behavior
Three mechanisms guarantee the `fail silent' behavior of the TJA1082:
* The TXEN Clamped flag is set if pin TXEN goes LOW for longer than tdetCL(TXEN) in
Normal mode; the transmitter will be disabled.
* The BGE Clamped flag is set if pin BGE goes HIGH for longer than tdetCL(BGE) in
Normal mode; no action will be taken.
* If a loss-of-ground occurs at the transceiver, resulting in the TJA1082 switching to
Power-off mode, no current will flow out of the digital input pins (TXD, TXEN, BGE, STBN, SCLK, SCSN); see Table 3 for details of the behavior of the bus pins.
6.6 TJA1082 flags and Status Register
The TJA1082 has 11 status/error flags. These are described in Table 7.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
13 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 7.
TJA1082 flags and set/reset conditions Set condition wake-up event on bus in Standby mode[2] Reset condition[1] transition to Normal mode leaving Normal mode transmitter disabled BGE LOW[5] transition to Normal mode Consequence of flag set RXD LOW; ERRN LOW [3] -
Flag name Flag type Flag description bus wake Normal mode status flag status flag indicates if a wake-up event has occurred
indicates if the transceiver entering Normal mode is in Normal mode indicates the transmitter status indicates if pin BGE is clamped indicates when the digital section is initialized transmitter enabled[4] BGE HIGH for longer than tdetCL(BGE)[5] VCC > Vth(rec)POR
transmitter status enabled flag BGE clamped PWON bus error status flag status flag error flag
indicates if a bus error has bus error detected[5] been detected indicates if the max. junction temperature has been reached indicates if pin TXEN is clamped indicates if there is an undervoltage at pin VCC indicates if there is an undervoltage at pin VIO indicates if an SPI error has occurred Tvj > Tj(dis)(high)[5]
no bus error detected or ERRN LOW [6] positive edge on TXEN[5] TXEN = HIGH while Tvj < Tj(dis)(high)[5] TXEN = HIGH[5] VCC > Vuvd(VCC) for longer than trec(uv)(VCC) VIO > Vuvd(VIO) for longer than trec(uv)(VIO) falling edge on SCSN ERRN LOW [6]; transmitter disabled ERRN LOW [6]; transmitter disabled ERRN LOW [6]; entering Standby mode ERRN LOW [6]; entering Standby mode ERRN LOW [7]
TEMP HIGH TXEN clamped UVVCC
error flag
error flag error flag
TXEN LOW for longer than tdetCL(TXEN)[5] VCC < Vuvd(VCC) for longer than tdet(uv)(VCC) VIO < Vuvd(VIO) for longer than tdet(uv)(VIO) SPI error detected[8]
UVVIO
error flag
SPI error
error flag
[1] [2] [3] [4] [5] [6] [7] [8]
All flags, with the exception of the PWON flag, are reset after a power-on reset. If an undervoltage has not been detected on pin VCC. If STBN = LOW. If BGE = HIGH, the Normal mode flag is set, the TEMP HIGH flag is not set and the TXEN clamped flag is not set. Flag can only be set or reset in Normal mode or on leaving Normal mode. If STBN = HIGH. If STBN = HIGH in SPI mode The SPI error flag is set when: a) more than 16 falling edges occur on pin SCLK while pin SCSN = LOW b) less than 16 falling edges occur on pin SCLK while pin SCSN = LOW.
The TJA1082 contains a 16-bit status register, of which bits S0 to S4 reflect the state of the status flags, bits S5 to S10 reflect the state of the error flags and bit S15 is a parity bit. All flags can be individually read out on pin SDO via a 16-bit SPI interface when the transceiver is configured in SPI mode. The status register bits are described in Table 8.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
14 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
TJA1082 status register Flag name Set condition bus wake Normal mode bus wake flag set Normal mode flag set Reset condition bus wake flag cleared Normal mode flag cleared transmitter enabled flag cleared BGE clamped flag cleared PWON flag cleared and successful readout[1] bus error flag cleared and successful readout[1] TEMP HIGH flag cleared and successful readout[1] TXEN clamped flag cleared and successful readout[1] UVVCC flag cleared and successful readout[1] UVVIO flag cleared and successful readout[1] SPI error flag cleared and successful readout[1]
Table 8. Status bit S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
[1]
transmitter transmitter enabled flag set enabled BGE clamped PWON bus error TEMP HIGH TXEN clamped UVVCC UVVIO SPI error reserved reserved reserved reserved parity bit BGE clamped flag set PWON flag set bus error flag set TEMP HIGH flag set TXEN clamped flag set UVVCC flag set UVVIO flag set SPI error flag set always LOW always HIGH always LOW always HIGH odd parity of status bits
even parity of status bits
Also cleared during Power-off.
6.7 Error signalling
The TJA1082 provides two modes for error indication:
* Simple error indication mode * SPI mode (default mode)
SPI mode is active on power-up. To switch to simple error indication mode, SCSN has to be held LOW (connected to GND) and SCLK held HIGH (connected to VIO) for longer than tdet(L)(SCLK) (provided an undervoltage has not occurred). When the TJA1082 is in simple error indication mode, a rising edge on SCSN initiates a transition to SPI mode (provided an undervoltage has not occurred).
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
15 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
SPI mode SCSN (V) VIO
simple error indication mode
SPI mode
0 t SCLK (V) VIO
0 t tdet(L)(SCLK)
015aaa015
Fig 11. State transitions timing (bus error flag set)
If an undervoltage condition is detected, it will not be possible to switch between SPI mode and simple error indication mode.
6.7.1 SPI mode
The error flag information in the status register is latched in SPI mode. This means that the status bit is reset once the status register has been completely read out (provided the corresponding error flag has been reset). If an error condition is detected in Normal mode, pin ERRN goes LOW (provided one of the error bits, S5-S10, is set). Pin ERRN goes HIGH again once all the error bits (S5-S10) have been reset.
6.7.2 Simple error indication mode
If an error condition is detected in Normal mode, pin ERRN goes LOW once the relevant error flag has been set. Pin ERRN goes HIGH again when all error conditions have been cleared and all flags have been reset. Error flags are not latched. It is not possible to read-out the status bits in this mode.
6.8 SPI interface
The TJA1082 includes a 16-bit SPI interface to enable a host to read the status register when the transceiver is in SPI mode (see Section 6.7). While pin SCSN is HIGH, the SDO output will be in a high-impedance state. To begin a status register readout, the host must force pin SCSN LOW. This will cause the SDO pin to output a LOW level by default. The data at pin SDO is then shifted out on the rising edge of the clock signal on pin SCLK. The status bits shifted out at SDO are active HIGH. The status bits are refreshed and pin SDO returned to a high-impedance state once the status register has been read successfully (after exactly 16 clock cycles) and SCSN has been forced HIGH again. Clock signals on SCLK will be ignored while SCSN is HIGH. The timing diagram for the SPI readout is illustrated in Figure 12. The SLCK period ranges from 500 ns to100 s (10 kbit/s to 2 Mbit/s)
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
16 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
If SCSN remains LOW for longer than 16 clock cycles, it recognized as an SPI error. When this happens, the SPI error flag is set and pin SDO goes to a high-impedance state until the next falling edge on pin SCSN. An SPI error will also be assumed if fewer than 16 clock cycles are received while SCSN is LOW. If this happens, the SPI error flag will be set. All status bits will be refreshed once the status register has been successfully read. When the transceiver is in simple error indication mode the SDO output will be in a high-impedance state and pin SCSN will be in pull-down mode. In SPI mode pin SCSN will be in pull-up mode. SPI readout is not possible when the transceiver has detected an undervoltage on VIO.
SCSN
tSPILEAD
TSCLK
tSPILAG
SCLK
01
02
03
15
16
td(SCSNHL-SDOL)
td(SCLKLH-SDODV)
td(SCSNLH-SDOZ)
SDO
Z
L
S0
S1
S2
S14
S15
Z
015aaa009
Fig 12. SPI readout timing diagram
7. Limiting values
Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol VCC VIO VERRN VRXD VSDO VTXEN VTXD VSTBN VSCSN VSCLK VBGE
TJA1082_1
Parameter supply voltage supply voltage on pin VIO voltage on pin ERRN voltage on pin RXD voltage on pin SDO voltage on pin TXEN voltage on pin TXD voltage on pin STBN voltage on pin SCSN voltage on pin SCLK voltage on pin BGE
Conditions no time limit operating range no time limit operating range no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit no time limit
Rev. 01 -- 1 July 2009
Min -0.3 4.75 -0.3 2.8 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
Max +5.5 5.25 +5.5 5.25 VIO + 0.3 VIO + 0.3 VIO + 0.3 +5.5 +5.5 +5.5 +5.5 +5.5 +5.5
Unit V V V V V V V V V V V V V
17 of 35
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 9. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol VBP VBM II(ERRN) II(RXD) II(SDO) Vtrt Tstg Tvj VESD Parameter voltage on pin BP voltage on pin BM input current on pin ERRN input current on pin RXD input current on pin SDO transient voltage storage temperature virtual junction temperature electrostatic discharge voltage IEC61000-4-2 on pins BP and BM to ground HBM on pins BP and BM to ground HBM on any other pin MM on all pins CDM on all pins
[1] [2]
[2] [3]
Conditions no time limit (with respect to pins BM and GND) no time limit (with respect to pins BP and GND) no time limit; VIO = 0 V no time limit; VIO = 0 V no time limit; VIO = 0 V on pins BP and BM
[1]
Min -60 -60 -10 -10 -10 -200 -55 -40 -8.0 -8.0 -4.0 -200 -1000
Max +60 +60 10 10 10 +200 +150 +150 +8.0 +8.0 +4.0 +200 +1000
Unit V V mA mA mA V C C kV kV kV V V
[4] [4] [5] [6]
According to ISO 7637, part 3 test pulses a and b; Class C; see Figure 17; Rbus = 45 ; Cbus = 100 pF. In accordance with IEC 60747-1. An alternative definition of virtual junction temperature Tvj is: Tvj = Tamb + TD x Rth(j-a), where Rth(j-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
[3] [4] [5] [6]
IEC61000-4-2: C = 150 pF; R = 330 .
HBM: C = 100 pF; R = 1.5 k. MM: C = 200 pF; L = 0.75 H; R = 10 . CDM: R = 1 .
8. Thermal characteristics
Table 10. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 130 Unit K/W
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
18 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
9. Static characteristics
Table 11. Static characteristics All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = -40 C to +150 C and Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Pin VCC ICC supply current Standby mode with no undervoltage; Tvj 85 C Standby mode with no undervoltage; Tvj 150 C Power-off mode; Tvj 85 C Power-off mode; Tvj 150 C Normal mode; VBGE = 0 V or VTXEN = VIO Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus 45 Normal mode; VBGE = VIO; VTXEN = 0; V; Rbus > 10 M Vuvd(VCC) Vuvr(VCC) Vuvhys(VCC) Vth(det)POR Vth(rec)POR Vhys(POR) Pin VIO IIO supply current on pin VIO Normal mode; VTXEN = VIO; VBGE = VIO; RRXD > 10 M Normal mode; VTXEN = 0 V; VBGE = VIO; RRXD > 10 M Standby mode with no undervoltage Power-off mode; VIO = 5 V Vuvd(VIO) Vuvr(VIO) Vuvhys(VIO) Pin SCSN VIH VIL HIGH-level input voltage LOW-level input voltage 0.7VIO -0.3 5.5 0.3VIO V V undervoltage detection voltage on pin VIO undervoltage recovery voltage on pin VIO undervoltage hysteresis voltage on pin VIO 2.6 2.62 20 3 3 1000 1000 7 7 2.779 2.799 190 A A A A V V mV undervoltage detection voltage on pin VCC undervoltage recovery voltage on pin VCC undervoltage hysteresis voltage on pin VCC power-on reset detection threshold voltage power-on reset recovery threshold voltage power-on reset hysteresis voltage 4.5 4.525 20 3.75 3.85 100 20 20 20 20 30 40 30 40 15 35 15 4.724 4.749 240 4.15 4.25 500 A A A A mA mA mA V V mV V V mV Parameter Conditions Min Typ Max Unit
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
19 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 11. Static characteristics ...continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = -40 C to +150 C and Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol IIH IIL Ir Pin SCLK VIH VIL IIH IIL Ir Pin STBN VIH VIL IIH IIL Ir Pin TXEN VIH VIL IIH IIL Ir Pin BGE VIH VIL IIH IIL Ir Pin TXD VIH VIL IIH IIL Ir HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current reverse current Normal mode Normal mode VTXD = 0.7VIO VTXD = 0 V Power-off mode; to VCC / VIO; VTXD = 5 V; VCC = VIO = 0 V 0.7VIO -0.3 3 -1 -5 0 0 VIO + 0.3 0.3VIO 15 +1 +5 V V A A A HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current reverse current VBGE = 0.7VIO VBGE = 0 V Power-off mode; to VCC / VIO; VBGE = 5 V; VCC = VIO = 0 V 0.7VIO -0.3 3 -1 -5 0 0 5.5 0.3VIO 15 +1 +5 V V A A A HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current reverse current VTXEN = VIO VTXEN = 0.3VIO Power-off mode; to VCC / VIO; VTXEN = 5 V; VCC = VIO = 0 V 0.7VIO -0.3 -1 -300 -5 0 0 VIO + 0.3 0.3VIO +1 -50 +5 V V A A A HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current reverse current VSTBN = 0.7VIO VSTBN = 0 V Power-off mode; to VCC / VIO; VSTBN = 5 V; VCC = VIO = 0 V 0.7VIO -0.3 3 -1 -5 0 0 5.5 0.3VIO 15 +1 +5 V V A A A HIGH-level input voltage LOW-level input voltage HIGH-level input current LOW-level input current reverse current VSCLK = VIO VSCLK = 0.3VIO Power-off mode; to VCC / VIO; VSCLK = 5 V; VCC = VIO = 0 V 0.7VIO -0.3 -1 -15 -5 0 0 5.5 0.3VIO +1 -3 +5 V V A A A Parameter HIGH-level input current LOW-level input current reverse current Conditions Simple error indication mode. VSCSN = 0.7VIO SPI mode; VSCSN = 0.3VIO Power-off mode; to VCC / VIO; VSCSN = 5 V; VCC = VIO = 0 V Min 3 -15 -5 Typ 0 Max 15 -3 +5 Unit A A A
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
20 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 11. Static characteristics ...continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = -40 C to +150 C and Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Ci Pin RXD IOH IOL Pin ERRN IOH IOL IL Pin SDO IOH IOL IL HIGH-level output current VSDO = VIO - 0.4 V LOW-level output current leakage current VSDO = 0.4 V high-impedance state; 0 V < VSDO < VIO Normal mode; VTXEN = VIO; Rbus = 45 Standby mode with no undervoltage on pin VCC Vo(idle)(BM) idle output voltage on pin BM Normal mode; VTXEN = VIO; Rbus = 45 Standby mode with no undervoltage on pin VCC Io(idle)BP Io(idle)BM Vo(idle)(dif) VOH(dif) VOL(dif) VIH(dif) VIL(dif) idle output current on pin BP idle output current on pin BM differential idle output voltage differential HIGH-level output voltage differential LOW-level output voltage differential HIGH-level input voltage differential LOW-level input voltage Normal and Standby modes with no undervoltage; -60 V VBP +60 V Normal and Standby modes with no undervoltage; -60 V VBM +60 V Normal mode; Rbus = 45 Normal mode; 40 Rbus 55 ; Cbus = 100 pF Normal mode; 40 Rbus 55 ; Cbus = 100 pF Normal mode; -10 V VBP +15 V -10 V VBM +15 V Normal mode; -10 V VBP +15 V -10 V VBM +15 V Standby mode with no undervoltage on pin VCC; -10 V VBP +15 V; -10 V VBM +15 V |Vi(dif)det(act)| activity detection differential input voltage (absolute value) -8 0.8 -5 -0.5 9 +5 mA mA A HIGH-level output current VERRN = VIO - 0.4 V; VIO = VCC LOW-level output current leakage current VERRN = 0.4 V VERRN VIO; VCC < Vth(det)POR -1500 200 -5 -100 1700 +5 A A A HIGH-level output current VRXD = VIO - 0.4 V; VIO = VCC LOW-level output current VRXD = 0.4 V -15 2 -1.7 20 mA mA Parameter input capacitance Conditions with respect to all other pins at ground; VTXD = 100 mV; f = 5 MHz
[1]
Min -
Typ -
Max 10
Unit pF
Pins BP and BM Vo(idle)(BP) idle output voltage on pin BP 0.4VCC -0.1 0.4VCC -0.1 -7.5 -7.5 -25 600 -1500 150 -300 -400 0.5VCC 0 0.5VCC 0 0 225 -225 -225 0.6VCC +0.1 0.6VCC +0.1 +7.5 +7.5 +25 1500 -600 300 -150 -125 V V V V mA mA mV mV mV mV mV mV
150
225
300
mV
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
21 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 11. Static characteristics ...continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = -40 C to +150 C and Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol |IO(sc)| Parameter short-circuit output current (absolute value) Conditions on pin BP; -5 V VBP +60 V on pin BM; -5 V VBM +60 V on pins BP and BM; VBP = VBM; -5 V VBP +60 V; -5 V VBM +60 V Ri(BP) Ri(BM) Ri(dif)(BP-BM) input resistance on pin BP Rbus = input resistance on pin BM differential input resistance between pin BP and pin BM input leakage current on pin BP Rbus = Rbus = Min Typ Max 35 35 35 Unit mA mA mA
10 10 20
20 20 40
40 40 80
k k k
ILI(BP)
Power-off mode; VCC = VIO = 0 V; 0 V VBP 5 V loss of ground; VBP = VBM = 0 V; all other pins connected to 16 V via 0
[1]
-5 -1600 -5
[1]
0 0 0.5VCC 0.5VCC 0 0
+5 +1600 +5 +1600 0.6VCC 0.6VCC +25 +300
A A A A V V mV mV
ILI(BM)
input leakage current on pin BM
Power-off mode; VCC = VIO = 0 V; 0 V VBM 5 V loss of ground; VBP = VBM = 0 V; all other pins connected to 16 V via 0
-1600 0.4VCC 0.4VCC -25 -300
Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage Vcm(bus) Vcm(act-idle) bus common-mode voltage difference active to idle common-mode voltage difference differential input volt. diff. betw. HIGH- and LOW-levels (abs. value) differential input voltage difference between HIGH-level and LOW-level input capacitance on pin BP input capacitance on pin BM differential input capacitance between pin BP and pin BM high disable junction temperature
Normal mode; Rbus = 45 Normal mode; Rbus = 45 Normal mode; DATA_1 - DATA_0; Rbus = 45 Normal mode; Rbus = 45
|Vi(dif)(H-L)|
(VBP + VBM)/2 = 2.5 V
-
-
10
%
Vi(dif)(H-L)
Normal mode; -10 V VBP +15 V -10 V VBM +15 V
-
-
60
mV
Ci(BP) Ci(BM) Ci(dif)(BP-BM)
with respect to all other pins at ground; VBP = 100 mV; f = 5 MHz with respect to all other pins at ground; VBM = 100 mV; f = 5 MHz with respect to all other pins at ground; VBP = 100 mV VBM = 100 mV; f = 5 MHz
[1]
-
-
15 15 5
pF pF pF
[1]
[1]
Temperature protection Tj(dis)(high) 180 200 C
[1]
Guaranteed by design.
(c) NXP B.V. 2009. All rights reserved.
TJA1082_1
Preliminary data sheet
Rev. 01 -- 1 July 2009
22 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
10. Dynamic characteristics
Table 12. Dynamic characteristics All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = -40 C to + 150 C and Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Pins BP and BM td(TXD-bus) delay time from TXD to bus Normal mode DATA_0 DATA_1 td(TXD-bus) td(bus-RXD) delay time difference from TXD to bus delay time from bus to RXD Normal mode; between DATA_0 and DATA_1 Normal mode; CRXD = 15 pF; (VBP + VBM)/2 = 2.5 V DATA_0 DATA_1 Normal mode; CRXD = 25 pF; (VBP + VBM)/2 = 2.5 V DATA_0 DATA_1 td(bus-RXD) delay time difference from bus to RXD Normal mode; between DATA_0 and DATA_1; (VBP + VBM)/2 = 2.5 V CRXD = 15 pF CRXD = 25 pF td(TXEN-busidle) td(TXEN-busact) |td(TXEN-bus)| delay time from TXEN to bus idle delay time from TXEN to bus active Normal mode; VTXD = 0 V Normal mode; VTXD = 0 V
[4] [3] [3] [1][2] [1][2]
Parameter
Conditions
Min
Typ
Max
Unit
-4
-
50 50 +4
ns ns ns
[3]
-
-
50 50
ns ns
-
-
60 60
ns ns
-5 -6 -
-
5 6 75 75 50
ns ns ns ns ns
delay time difference from TXEN to bus Normal mode; between TXEN (absolute value) to bus active and TXEN to bus idle; VTXD = 0 V delay time from BGE to bus idle delay time from BGE to bus active bus differential rise time Normal mode; VTXD = 0 V Normal mode; VTXD = 0 V DATA_0 to DATA_1; 20 % to 80 %; Rbus = 45 ; Cbus = 100 pF DATA_1 to DATA_0; 80 % to 20 %; Rbus = 45 ; Cbus = 100 pF on bus; 80 % to 20 % Rbus = 45 ; Cbus = 100 pF bus idle to DATA_0; Rbus = 45 ; Cbus = 100 pF; -30 mV > Vdif > -300 mV DATA_1 to bus idle; Rbus = 45 ; Cbus = 100 pF; 300 mV > Vdif > 30 mV
td(BGE-busidle) td(BGE-busact) tr(dif)(bus)
[5]
-
75 75
ns ns
3.75
18.75 ns
tf(dif)(bus)
bus differential fall time
[5]
3.75
-
18.75 ns
t(r-f)(dif) tf(bus)(idle-act)
difference between differential rise and fall time bus fall time from idle to active
[5]
-3 -
-
3 30
ns ns
[5][6]
tf(bus)(act-idle)
bus fall time from active to idle
[5][6]
-
-
30
ns
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
23 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 12. Dynamic characteristics ...continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = -40 C to + 150 C and Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol tr(bus)(act-idle) Parameter bus rise time from active to idle Conditions DATA_0 to bus idle; Rbus = 45 ; Cbus = 100 pF; -300 mV < Vdif < -30 mV Standby mode with no undervoltage on pin VCC; -10 V VBP +15 V; -10 V VBM +15 V Standby mode with no undervoltage on pin VCC; -10 V VBP +15 V; -10 V VBM +15 V Standby mode with no undervoltage on pin VCC; -10 V VBP +15 V; -10 V VBM +15 V Standby mode with no undervoltage on pin VCC; -10 V VBP +15 V; -10 V VBM +15 V 0 V VIO 5.5 V; VCC = 4.4 V 0 V VIO 5.5 V; VCC = 4.85 V Vth(det)POR < VCC < 5.5 V; VIO = 2.5 V Vth(det)POR < VCC < 5.5 V; VIO = 2.9 V Normal mode; Vdif: 0 mV 400 mV; (VBP + VBM)/2 = 2.5 V Normal mode; Vdif: 400 mV 0 mV; (VBP + VBM)/2 = 2.5 V Normal mode; on bus pins; (VBP + VBM)/2 = 2.5 V Normal or Standby mode with no undervoltage on pin VIO Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF
[9] [6] [5][6]
Min -
Typ -
Max 30
Unit ns
Wake-up detection tdet(wake)DATA_0 DATA_0 wake-up detection time
[7]
1
-
4
s
tdet(wake)idle
idle wake-up detection time
[7]
1
-
4
s
tdet(wake)tot
total wake-up detection time
[7]
50
-
115
s
tsup(int)wake
wake-up interruption suppression time
[8]
130
-
-
ns
Undervoltage tdet(uv)(VCC) trec(uv)(VCC) tdet(uv)(VIO) trec(uv)(VIO) undervoltage detection time on pin VCC undervoltage recovery time on pin VCC undervoltage detection time on pin VIO undervoltage recovery time on pin VIO 2 2 5 5 100 100 100 100 s s s s
Activity detection tdet(act)(bus) activity detection time on bus pins 100 250 ns
tdet(idle)(bus)
idle detection time on bus pins
[6]
100
-
250
ns
|tdet(act-idle)|
active to idle detection time difference (absolute value) LOW-level detection time on pin SCLK
-
-
150
ns
ERRN signalling tdet(L)(SCLK) SPI td(SCSNHL-SDOL) SCSN falling edge to SDO LOW-level delay time 250 ns 95 310 s
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
24 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
Table 12. Dynamic characteristics ...continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = -40 C to + 150 C and Rbus = 45 unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF 20 % to 80 %; CRXD = 15 pF 20 % to 80 %; CRXD = 25 pF tf t(r-f) Bus error flag td(norm-stb) td(stb-norm) Miscellaneous tdetCL(TXEN) tdetCL(BGE)
[1] [2] [3] [4] [5] [6] [7] [8] [9]
[9]
Min -
Typ -
Max 200
Unit ns
td(SCLKLH-SDODV) SCLK rising edge to SDO data valid delay time td(SCSNLH-SDOZ) SCSN rising edge to SDO three-state delay time SCLK period
[9]
-
-
500
ns
TSCLK
[9]
0.5
-
100
s
tSPILEAD
SPI enable lead time
[9]
250
-
-
ns
tSPILAG
SPI enable lag time
[9]
250
-
-
ns
RXD tr rise time fall time difference between rise and fall time
[4] [4] [4] [4] [4] [4]
-4 -7 3 3 1500 1500
-
5 9 5 9 4 7 10 10 2600 2600
ns ns ns ns ns ns s s s s
80 % to 20 %; CRXD = 15 pF 80 % to 20 %; CRXD = 25 pF CRXD = 15 pF CRXD = 25 pF
normal mode to standby delay time standby to normal mode delay time TXEN clamp detection time BGE clamp detection time
bus error flag set bus error flag set 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V
Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 1 ns. See Figure 14. See Figure 15. Guaranteed by design. See Figure 17. Vdif = VBP - VBM. See Figure 8. See Figure 10. See Figure 12.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
25 of 35
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Preliminary data sheet Rev. 01. -- 1 July 2009
(c) NXP B.V. 2009. All rights reserved. TJA1082_1
www..com
NXP Semiconductors
td(TXD-bus0) td(TXD-bus1) td(TXEN-busidle)
td(TXEN-busact) td(BGE-busidle)
td(BGE-busact)
TXD
0.5VIO
TXEN
0.5VIO
BGE
0.5VIO
BP and BM
+300 mV 0V -300 mV
80 % -30 mV -300 mV -30 mV -300 mV 20 %
RXD
0.5VIO
td(bus-RXD)
td(bus-RXD)
tdet(idle)(bus)
tdet(act)(bus) tr(busact-busidle) tf(busact-busidle)
tr(dif)(bus)
tf(dif)(bus)
015aaa010
Fig 13. Detailed timing diagram
FlexRay node transceiver
TJA1082
26 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
> 100 ns TXD 100 % of VIO 50 % of VIO 0 % of VIO td(TXD-bus) Vdif(VBP-VBM) (mV) > 600 300 0 t -300 < -600 tf(dif)(bus) tr(dif)(bus)
015aaa011
t td(TXD-bus)
100 % 80 %
20 % 0%
Vdif is the transmitter test signal.
Fig 14. Transmitter timing diagram
Vdif(VBP-VBM) (mV) 22 ns 400 300 22 ns
0
-300 -400 30 ns RXD 100 % VIO 80 % VIO 50 % VIO 20 % VIO 0 % VIO tf(RXD) tr(RXD)
015aaa012
30 ns
30 ns
td(bus-RXD)
td(bus-RXD)
Vdif is the receiver test signal.
Fig 15. Normal receiver timing diagram
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
27 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
11. Test information
+5 V
100 nF
1 VIO
14 VCC BP 13
Rbus Cbus
TJA1082
BM
12
RXD
015aaa013
4
CRXD
Fig 16. Test circuit for dynamic characteristics
+5 V
100 nF
1 VIO
14 VCC BP 13
Rbus 1 nF
Cbus
TJA1082
BM RXD
12
1 nF
ISO 7637 PULSE GENERATOR
4
15 pF
015aaa014
The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 4 and 5. Test conditions: Normal mode: bus idle Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz
Fig 17. Test circuit for automotive transients
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
28 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
12. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 18. Package outline SOT402-1 (TSSOP14)
TJA1082_1 (c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
29 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
TJA1082_1 (c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
30 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14
Table 13. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 14. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19.
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
31 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
32 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
14. Abbreviations
Table 15. CAN CDM ECU EMC EME EMI ESD HBM MM PWON Abbreviations Description Controller Area Network Charged Device Model Engine Control Unit ElectroMagnetic Compatibility ElectroMagnetic Emission ElectroMagnetic Immunity ElectroStatic Discharge Human Body Model Machine Model Power-on Abbreviation
15. References
[1] [2] EPL -- FlexRay Communications System Electrical Physical Layer Specification Version 2.1 Rev. B, FlexRay Consortium, Nov 2006 AN -- Application hint AN10365 - Surface mount reflow soldering description
16. Revision history
Table 16. TJA1082_1 Revision history Release date 20090701 Data sheet status Preliminary data sheet Change notice Supersedes Document ID
TJA1082_1
(c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
33 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
17. Legal information 18. Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.1 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
18.2 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
18.3 Licenses
Purchase of NXP ICs with FlexRay functionality FlexRay license required. This product has been developed within the framework of the "FlexRay" consortium. FlexRay consortium members are willing to grant licenses under their essential FlexRay intellectual property rights to end users of FlexRay-enabled products upon request of an end user. The sale by NXP Semiconductors of a FlexRay-enabled product will not be construed as the granting of such a license. Each end user will have to apply to the FlexRay consortium administration to obtain such a license or to apply for membership. The FlexRay consortium can be contacted at request@flexray.com.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1082_1 (c) NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 -- 1 July 2009
34 of 35
www..com
NXP Semiconductors
TJA1082
FlexRay node transceiver
20. Contents
1 2 2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Optimized for time triggered communication systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Low power management . . . . . . . . . . . . . . . . . 1 2.3 Diagnosis and robustness . . . . . . . . . . . . . . . . 2 2.4 FlexRay conformance classes . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1.1 Bus activity and idle detection . . . . . . . . . . . . . 6 6.1.2 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.3 Power-off mode. . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.4 State transitions . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Power-up and power-down behavior . . . . . . . . 9 6.2.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 Remote wake-up. . . . . . . . . . . . . . . . . . . . . . . 11 6.3.1 Bus wake-up via wake-up pattern. . . . . . . . . . 11 6.3.2 Bus wake-up via dedicated FlexRay data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.4 Bus error detection . . . . . . . . . . . . . . . . . . . . . 13 6.5 Fail silent behavior . . . . . . . . . . . . . . . . . . . . . 13 6.6 TJA1082 flags and Status Register . . . . . . . . 13 6.7 Error signalling . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7.1 SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.7.2 Simple error indication mode . . . . . . . . . . . . . 16 6.8 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Thermal characteristics. . . . . . . . . . . . . . . . . . 18 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 23 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 28 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29 13 Soldering of SMD packages . . . . . . . . . . . . . . 30 13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 30 13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 30 13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 30 13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15 16 17 18 18.1 18.2 18.3 18.4 19 20 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 34 34 34 34 34 34 34 35
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 July 2009 Document identifier: TJA1082_1

▲Up To Search▲

Price & Availability of TJA1082

	To Download TJA1082 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .